Conventional PLA Operation
Performing logic functions in an array of identical circuit elements each located at a unique intersection of an input and output line in a grid of intersecting input and output lines is well-known. It is also well-known to perform complex logic functions in a compound arrangement of these arrays called a programmable logic array chip (PLA) by using the outputs of one array as the inputs to another array. U.S. Pat. No. 3,936,812 by Cox, et al. describes such a PLA on which a number of decoders feed inputs to a first array called a product term generation or an AND array which in turn supplies outputs to a second array called a sum of product term generator or an OR array. The outputs of the OR array are then used to control the setting and resetting of a string of latches so that both combinatorial and sequential logic functions can be performed by the PLA. The particular logic functions actually performed by the given PLA are controlled by the locations and number of the active logic circuits in the AND and OR arrays of the PLA and also by how inputs are supplied to the decoders either from off the chip or from the latches. In the Cox, et al. type PLA circuitry shown for the example in FIG. 1, each binary variable A and B undergoes a two-bit partitioning to yield four input lines AB, AB, A B, and AB. An input line 6 will be active for a particular product term line 2 only if the gate and thin oxide for the corresponding MOSFET array device 8 was formed during manufacture. FIG. 1 shows such active array devices 8 for the input lines A.sub.1 B.sub.1, A.sub.1 B.sub.1, A.sub.2 B.sub.2, A.sub.2 B.sub.2, A.sub.3 B.sub.3, A.sub.3 B.sub.3, connected to the product term line 2. The other array devices 10 in FIG. 1 did not have their respective gate and thin oxide formed during manufacture and are therefor inactive in this circuit. To carry out an operation, for example determining the condition that a number of pairs of variables are equal, positive logic would test the condition AB and the condition A B and if either condition is satisfied, then both A and B would be equal. However, the Cox, et al. circuitry is a negative logic circuitry. By that it is meant that the product term line 2 for the AND array of FIG. 1 is precharged through charging FET 4 to a positive value when clock line MS goes positive. When a charging condition appears on any gate of an array device 8 in the AND array, the vertical product term line 2 from the AND array is discharged to the ground line 12, dropping the potential at the corresponding connected gate of the OR array connected to the product term line 2. Since the drain lines for the OR array elements are precharged to a positive value, if the OR array gate is grounded, then there will be no change to the output latch. Therefore, negative logic has to be applied so that a change will be made to occur at the output latch. Thus, if one desired to determine when A is equal to B, one applies the terms AB and AB to the gates of vertically juxtaposed FET devices 8 in the AND array connected to the same product term line 2, as shown in FIG. 1, so that if either one of those two input lines 6 is on, then the corresponding product term potential drops on line 2, the connected OR array gate is rendered nonconductive, and thus no change is made to the output latch. A lack of change in the output latch indicates that the input binary variables A and B are not equal. Correspondingly if the input variables A and B are equal, then a change will be seen to occur in the output latch. This is the conventional way to operate the Cox, et al. PLA.
Where four variables which are paired as the group A.sub.1 and B.sub.1 and the group A.sub.2 and B.sub.2 are to be examined to determine whether A.sub.1 and B.sub.1 are equal and then whether A.sub.2 and B.sub.2 are equal, one merely replicates the illustration above for A.sub.2 and B.sub.2. To determine whether A.sub.1 and B.sub.1 are equal and also whether A.sub.2 and B.sub.2 are equal, one merely applies the outputs A.sub.1 B.sub.1 and A.sub.1 B.sub.1 and A.sub.2 B.sub.2 and A.sub.2 B.sub.2 to AND array elements which are vertically juxtaposed on the same product term line 2 as shown in FIG. 1, since an AND operation is desired. FIG. 1 shows the arrangement for pairs: A.sub.1 B.sub.1, A.sub.2 B.sub.2, and A.sub.3 B.sub.3.